A Yokogawa 40G pulse pattern generator (AP9950) generates a 43Gbps data signal and a 43 GHz clock signal. This is done by means of a 4:1 MUX (B9977YG) which multiplexes four 10Gbps signals to 40Gbps.

The data and clock signals are applied to a modulator driver (B9977XT) to drive the LN modulator. This module includes a DFF function that re-times and re-shapes the data signal just before it is applied to the LN modulator.

The full-WDM-band photodiode receives the optical signal after it passes through a 40 km NZDSF fiber, DCF fiber and an EDFA optical amplifier. This photodiode module uses a transe-impedance amplifier (TIA) and a limiting amplifier (LA), and generates the output signal to a subsequent logic module.

The CDR recovers the clock and data signals, which are applied to a Yokogawa 40G Error Detector (AP9951) for BER measurement. A 1:4 demultiplexer (B9977YH) is installed on the AP9951.