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Bit Error Rate Tester

AQ2200-601
Features
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FeaturesMainframe ScreenshotExample ApplicationsSpecifications
 
• Optimize the use of lab bench space
• Take measurements in close proximity to the system/device being measured
• Easily portable

The AQ2200-601 integrates a pulse pattern generator (PPG), error detector (ED) and signal generator (SG) in a compact module, so a single unit can handle bit error rate (BER) measurements. The AQ2200 series has all the modules you need for optical device/system characterization, including optical modulators, receivers, power meters, and attenuators. The AQ2200 Series also includes equipment designed especially for using the 10 Gbit/s band BERT standalone function (using the AQ2201 3-slotmainframe). The small size and light weight of the AQ2200-601 provides the following advantages:


  • PPG function
    • Support for multiple bit rates:
      9.95 Gbit/s to 11.32 Gbit/s, variable in steps of 1 kHz
    • Output amplitude:
      0.5 Vp-p to 2.0 Vp-p, variable in steps of 10 mV
    • Offset:
      -2.0 V to +3 V, variable in steps of 10 mV
    • Crosspoint:
      30% to 70%, variable in steps of 1%
    • Data and data bar:
      2 outputs
    • Trigger output for oscilloscope synchronization
    • Port for external 10 G clock synchronization input and 1/16 or 1/64 synchronization input
      It is possible to perform an error rate test with jitter deliberately added to the data pattern by inputting a synchronization signal with added jitter to this port.

  • Bit error rate test (BERT)
    A BERT is a type of code error measurement made through digital communication using a PPG as the signal source and an ED as the error detector.
    BERT

  • ED function
    • CDR function included as standard feature
      The CDR signal extracts the clock from the data signal and performs synchronization when a data signal is the only input. In optical communications, the CDR function is a useful tool because the data signal is often transmitted alone.
    • In addition to the CDR input port, there are ports for inputting separate data and clock signals. When these ports are used, the phases of the data and clock signals must be matched externally.
    • Input ranges:
      0.1 Vp-p to 0.7 Vp-p (with CDR), 0.1 Vp-p to 0.6 Vp-p (without CDR)

  • Test patterns
    • There are two types of test patterns: pseudo-random (PRBS) patterns and program patterns.
    • The PRBS pattern is selected from settings ranging from PRBS7 to PRBS31.
    • In the standard configuration, the AQ2200-601 program pattern consists of 256 bits. A 64 Mbit option is also available.

  • Supported bit rates
    Network nameStandard Standard bit rateFEC
    SDH/SONET STM-64/OC-192 9.953280 Gbit/s 10.664228 Gbit/s
    STM-16/OC-48 10.796778 Gbit/s
    10G Ethernet 10 GBASE-R 10.312500 Gbit/s 11.095728 Gbit/s
    Fibre Channel 10 G-FC 10.518750 Gbit/s 11.317642 Gbit/s
    OTN OTU2 10.709225 Gbit/s

BERT screen
BERT screen

1. Measurement status display
 1-1 Elapsed time display
:Displays the elapsed time
 1-2 Logging display
: Displays an indicator which indicates the logging execution status
 1-3 Operation status display
: System clock error: Displays the system clock status
Err on: Displays the PPG error addition ON/OFF status
OutputDisplays the PPG output signal ON/OFF status
CDR ulk:Displays the ED CDR function operation status
Sync-los:Displays the ED synchronization status
Bit-err:Displays the ED bit error detection status
 1-4 Measurement result display
: Syn-los: Displays the ED synchronization loss time (in microseconds)
Err-cnt:Displays the ED received data error count (in bits)
Err-rate:Displays the ED received data error rate as a numerical value
2. Function keys start mes
  Starts measurement
Stop mes:Stops measurement
Error add:Turns error addition ON/OFF
Signal output: Turns PPG data output and clock output ON/OFF
Information: Displays the firmware version and other information
3. Setting display
  Displays the settings. Use the tab key to switch the display
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