VLSI Test System TS6000H+

	Home / Our Businesses / Semiconductor.. / LSI Test System / SoC Ｔｅｓｔ Syst.. /
	VLSI Test System TS6000H+

Realization of a huge cost reduction on System-On-A-Chip Devices Testing.

VLSI Test System TS6000H+

Reduce turn-around time

Drastic Reduction in Turn-Around Time from Design to Test

The TS6000H offers test development solutions that achieve a drastic reduction in the turn-around time from design to test and significantly increase test rates and the number of test pins, enabling wider device coverage. This allows test debug to be done prior to the process-out of the engineering sample devices, as well as reduction of design time through the hardware/software coordinated verification, completely changing the conventional concept of the whole stage from device development to test. Measurement with superior cost performance in a wide variety of fields is possible with RF options and analog options.

Features & Performance

	Cost-performance Cost-sensitive and performance-oriented design scheme achieves superior cost-performance -- three times better than that of equivalent test systems in the market.
	Drastically reduced time through design to test The ability to debug devices before their completion and the use of hardware/software coordinated verification significantly accelerate the entire design process, from device development to testing.
	Compatible for Mixed Signal SoC Devices In addition to being equipped with AWG and DIGITIZER (HRG/D, HSG/D) of analog modules, this system now includes the RF SUB system and SHFSM, enabling measurement of SoC devices such as RFCMOS.
	750MHz data rate, 768 pins The data rate has drastically increased to 750MHz. The number of test pins has also up to 768, allowing testing of higher-speed and larger-scale devices.
	Pattern generation at up to 660MHz data rate The system can generate high-speed data patterns (maximum 660 MHz), allowing high-speed serial interface testing of LVDS devices. This was not possible with general-purpose test systems.
	Large-capacity pattern memory (128MW) This system has a 128MW pattern memory, which is twice the capacity of other test systems in the same class; this enables the testing of large-scale devices with advanced functions.
	Analog Options High Speed digitizer (12bit,100MSPS) High Resolution digitizer (18bit,1MSPS) High Speed Generator (14bit,300MSPS) High Resolution Generator (16bit,10MSPS) RF Source (250 kHz to 6 GHz, modulation 2 ch) RF Measurement (SLM format, 100 Hz to 6GHz, max. 2 ch)
	AViPS™ – Testing Support System Software (Optional) AViPS™ offers powerful support for device evaluation and test debugging. AViPS™ has a variety of visual application tools, which allows data to be efficiently shared between tools.

Target devices:
	Large-scale system-on-a-chip devices (with built-in memory, MPU and AD/DA), largescale high-speed ASIC, ASSP such as DVD, high-speed MCU, MPU, High-speed I/F devices, SoC for digital TVs, RFCMOS onechip IC (RF Transceiver and the like)

Data rate:

max. 750MHz

Number of pins:

max. 768

Overall timing accuracy(OTA):

350ps