| We are meeting the market's demand for the rapid delivery of high-performance devices at lower than ever prices. This could not be accomplished without low-cost device testing systems that have a short turn around time. |
| 1. Tester Plus DFT Solutions |
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This chart shows the progression of device performance and tester cost over time. The red arrow represents device performance and the yellow arrow tester costs.
With testers the challenge has always been keeping up with semiconductor device performance. It is becoming more difficult than ever to test devices at speed and at low cost. Cost is the most crucial issue.
SoCs include large scale DRAM, analog functions, and various IPs. A suitable test system for such devices must be equipped with high-speed digital functions in excess of 1GHz and support huge pin counts of 1000 or more. Test systems in this class typically cost several million US dollars or more, an expense that is becoming increasingly difficult to justify given the increasing price competition in the device business. Despite this dilemma, devices continue to evolve.
How do we cope with this issue? What will test methodologies be like in 2010? We believe that a totally new approach will be necessary and that a versatile and dependable technology called Built-In Self-Test (BIST) will provide the solution. Also part of this solution will be Build-Off Self-Test (BOST) technology, which is both handy and affordable, and Structural Design-for-Test (DFT).
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| 2. High-speed serial pattern generation IP |
| With a high timing accuracy of 500ps, the TS6000 System LSI Test system supports testing speeds of 200MHz or more when used with Yokogawa Test IP. This is a low cost solution that achieves speeds which previously were only possible with test systems in the $1 million plus range. |
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| 3. Some difficulties in reducing turn around time |
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It now takes more time to get from the mask design phase to the engineering sample (ES) ready stage, and it is unacceptable if the entire process from design to production start takes longer than once month. A major factor impeding rapid development is the inherent differences between the design and prototyping/production processes.
The above flowchart shows the evaluation process, from IC design verification to the ES and mass production stages. The yellow box represents the design phase and the white box the testing phase. During the design phase, everything takes place in the virtual domain, with design verification performed by simulators, virtual ICEs, and virtual testers. In the production phase, actual electric signals from samples and mass production devices can be evaluated by testers.
The gap between the virtual evaluation environment and the actual test environment is significant, and it complicates the task of reducing turn around time. V-R TestPlanner is an important asset in bridging the gap between these two environments and reducing turn around time.
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| 4. V-R TestPlanner™ reduces turn around time (TAT) |
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V-R TestPlanner is a valuable testing asset that significantly reduces turn around time (TAT). An important component of this package is the Virtual ICE tool, which enables comprehensive device test verification including co-verification and IP/BIST simulation.
As shown in the above illustration, Virtual ICE can be used to conduct an engineering sample (ES) evaluation before the actual ES is available, reducing the LSI design time by two-thirds. Virtual ICE can also generate functional test vectors with tester timing frames.
A virtual tester (TS Virtualizer Plus) brings together the virtual and actual worlds. This tool can perform a test simulation without the actual ES, using a model of the device architecture. Testing of the actual ES prototype is subsequently done through the virtual tester, using the TS6000H+.
The virtual tester bridges the gap between the real and virtual test environments discussed in previous pages and reduces turn around time by one-half. The TS6000H+ provides both high performance and the ability to function together with this virtual environment. |
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