V-R TestPlanner

Test support system for large-scale system-on-a-chip devices

V-R TestPlanner™

V-R TestPlanner

V-R TestPlanner, the test support system for large-scale system-on-a-chip devices, offers new test engineering solutions that reduce both time to market and test costs. With V-R TestPlanner, test program debugging can be done virtually, before device completion. This reduces test debugging time and greatly facilitates the device design process because any problems discovered during the test program development phase can be communicated back to the device designers before they complete the device design.

Features & Performance

	Allows test program debugging using a Verilog simulator in a virtual test environment (applies also to the ATE and DUT models)
	Allows correction of coding errors and checking of test system operating range
	Allows test pattern validity checks and pattern changes before tests are run
	Uses the same operating screens for both real and virtual test systems
	Allows transfer of test information between real and virtual test systems
	Enables IC designers and test engineers to share the same test environment