KOMACHI Tomonori1 TAKAYAMA Tadahiko2 IMAMURA Makoto1
To develop a small and high-breakdown voltage semiconductor relay for scanners in recorders, we have developed a MOSFET (metal-oxide-semiconductor field-effect transistor) with a new three-dimensional termination as a switching device. The termination consists of deep-etched side-walls and junctions on them. Using this structure, a 3200 V MOSFET measuring just 1.7 mm-square has been achieved for the first time in the world. We used a MEMS (micro electro mechanical systems) process to etch a 400-μm groove, which is several ten to several hundred times as deep as that formed by a normal dry etching process.
- Advanced Device Development Div., Corporate R&D Headquarters
- Product Business Center, Industrial Automation Business Headquarters
Introduction
In 1989, Yokogawa released a recorder equipped with semiconductor relays of 1500 V breakdown voltage for the first time in the world.1 2 Based on this technology, Yokogawa has developed a semiconductor relay with ultra- low capacitance for LSI testers.3 Cumulative sales of the semiconductor relays have since exceeded ten million channels, gaining an excellent reputation.
However, relays for scanners integrated in recorders used in the production field require greater tolerance to voltage surges. In addition, in the latest IEC61010-2001 safety standard, an insulation voltage of 3170 V is required for measuring instruments connected to 200 V-class power sources. Therefore, a high-breakdown voltage of 3200 V is required for relays used in instruments measuring 200 V-class hot lines which are commonly used worldwide.
Design of High-Breakdown Voltage
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| Figure 1 Configuration of a semiconductor relay |
Configuration of a semiconductor relay
The configuration of a semiconductor relay is shown in Figure 1. The input signal makes the light emitting diode (LED) emit light, the emitted light is converted to voltage by a voltage output type photodiode array, and then the voltage is applied to the gate of the metal-oxide-semiconductor field- effect-transistor (MOSFET). A pair of MOSFETs is connected in series to accept both positive and negative signals. A shunt resistor is inserted between the source and gate of the MOSFET to discharge the charge which has accumulated on the gate, when the semiconductor relay is switched from the on-state to the off-state. One of the devices to which a high voltage is directly applied in the semiconductor relay is the MOSFET. Therefore, it is designed to withstand high voltages even when the voltage is applied between the source and drain when the MOSFET is in the off-state.
Conventional structure of high-breakdown voltage
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Figure 2 Conventional lateral MOSFET |
MOSFET Currently, Yokogawa is using lateral MOSFETs in which current f lows horizontally along a device as indicated in Figure 2. Its breakdown voltage is 1500 V, leakage current at 100 V is about 400 pA, and off-state capacitance is 70 pF. The breakdown voltage of 1500 V is realized by a bi-directional switch consisting of two FETs. The chip size is 3.4 mm by 1.7 mm.
In order to achieve the breakdown voltage of 3200 V using the conventional lateral MOSFET structure, the impurity concentration of the conductive area (area between source and drain) should be lowered and the distance should be increased by three times. In addition, in order to compensate the increased resistance caused by the lowered impurity concentration and increased distance of the conductive area, the conductive area should be widened laterally. Therefore, the chip will inevitably be larger.
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| Figure 3 Structure of termination region of a conventional vertical MOSFET |
On the other hand, although a vertical MOSFET in which current flows vertically through a device requires small conductive area, field rings should be placed at appropriate distances in order to maintain the breakdown voltage by enlarging the depletion layer, as shown in Figure 3. This area is called the termination region, and it is several times as large as the conductive area.
The above design increases the junction area, impairing the characteristics of low leakage current which is important in applications like scanners. Also, the increase of chip dimensions increases the package size, which is undesirable in terms of cost and resources.
New structure of termination region of a vertical MOSFET
Conventionally, devices have been considered in two dimensions and high-breakdown voltages have been attempted by devising the structure of the termination region of the upper surface, thus limiting the increase in breakdown voltage. However, we focused on decreasing the chip size by merely eliminating the termination region of the vertical MOSFET considering the structure in three dimensions.
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Figure 4 Operating principle of new structure of termination region |
When the surroundings of a conductive area of a device are dug vertically and deeply, not only do the dimensions of the chip decrease but also the junction becomes an ideal parallel plane junction. Thus, the breakdown voltage approaches the theoretical value. In an actual device, however, the side of the device must be covered with a protective coat such as an oxide film to maintain stable characteristics. As a result, as shown in Figure 4 (a), interface charges (Qss) arising at the boundary between silicon and oxide film prevent the expansion of the depletion layer, and so the breakdown voltage decreases.
Consequently, we have formed a vertical p - layer between the oxide film and the n - layer of silicon as shown in Figure 4 (b). The whole vertical p - layer changes to the depletion state when a relatively low reverse-bias voltage is applied. When the bias voltage is increased, the depletion layer expands from the upper main PN junction toward the n - layer, and at the same time the depletion layer grows bigger from the vertical junction in bulk of the n - layer, thus the whole n - layer can be effectively changed to the depletion state. This is the basic principle of achieving a high breakdown voltage in spite of the small chip dimensions.
Designing the MOSFET with new structure of termination region
A cross-sectional view of the MOSFET with the new structure of termination region is shown in Figure 5. The side of the device is surrounded by the structure previously mentioned, and the upper surface is configured by repeated small FETs called cells in the same way as the normal vertical MOSFET.
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Figure 5 New structure of termination region of vertical MOSFET |
The design of the vertical MOSFET involves designing the substrate, termination region and FET cells. W hen designing the substrate, the same as when designing punch- through diodes, the breakdown voltage BV is given by the equation using substrate density NA , width of depletion layer W and electric field EC.
(Where q is the unit charge value, εS is dielectric constant of silicon)
Using this equation, we decided each parameter so as to minimize the specific resistance while maintaining the desired breakdown voltage.
When designing the termination region, we investigated the density and width of the vertical p - layer by simulation, so that the fundamental breakdown voltage depending on the substrate does not drop at the termination region. We then selected the optimum value by experiment.
When designing FET cells, we conducted a simulation changing such parameters as gate length and source length, and decided them taking the balance of breakdown voltage and on-resistance into consideration.
Fabricating Process
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| Figure 6 Flow of fabricating process |
For the wafers of the prototype, a direct bonding wafer was used to obtain both high breakdown voltage and low on- resistance. A wafer 350 μm thick with high resistance was stuck on the support substrate with low resistance; this is thick enough to be handled even after deep etching. The outline of the fabricating process flow is shown in Figure 6.
- Form FET cells on the surface of the wafer as the normal vertical MOSFET
- Etch grooves of 400 μm depth and 300 μm width around the chip applying inductively coupled plasma-reactive ion etching (ICP-RIE) process. Recently, ICP-RIE is frequently utilized in micro electro mechanical systems (MEMS) fabrication. The appearance of the device after etching is shown in Figure 7. The inclination of its side surface is 91 degrees and its roughness is 200 nm or less.
- Flatten the side surface and make it grow epitaxially.
- Remove the excess epitaxial growth by etching, and form a protective oxide film over it.
- Because of the deep grooves, coat the resist for patterning of electrodes on the upper surface using a spray coater.
- Dice-cut the wafer along the grooves etched by ICP-RIE (f) and separate it into chips.
Result of the Prototype
An overall view of the completed 1.7 mm square MOSFET is shown in Figure 8. The observed step outside of the chip is the result of grooving and cutting within ICP-RIE and dicing processes. As for electrodes, there are a gate and a source on its surface and a drain on its back, which are the same as those of the normal vertical MOSFET.
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Figure 7 Appearance of the device after |
Figure 8 Appearance of the completed chip |
The breakdown characteristics are shown in Figure 9. We could achieve a breakdown voltage of 3200 V and leakage current of 1.2 nA at 200 V. The on-resistance was 165 W and threshold voltage was 1.6 V.
Figure 10 shows the relation between breakdown voltage and normalized on-resistance. A high breakdown voltage and low on-resistance are contradictory characteristics, and there exists the "silicon limit" of silicon used for the substrate. In Figure 10, devices further to the right and lower are better. The developed device is significantly better than the conventional small high-breakdown-voltage MOSFET. Overall, the chip including the termination region is located close to the "silicon limit," confirming that this configuration delivers on-resistance close to the theoretical limit with small size and high breakdown voltage.
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Figure 9 Breakdown characteristics |
Figure 10 Performance comparison of high-breakdown voltage MOSFETs |
Conclusion
We have succeeded in creating a small MOSFET measuring 1.7 mm square with the characteristics of breakdown voltage of 3200 V, on-resistance of 165 W, and leakage current of 1.2 nA at 200 V. With the technology introduced in this paper, the termination region on the chip surface is no longer necessary, and the small MOSFET measuring a few millimeters square offers a high-breakdown voltage of several thousand volts.
In future, we will address the issue of output capacity. The output capacity of this prototype is three to five times bigger than that of the conventional product. However, our recent simulation shows that the output capacity could be made smaller than that of the conventional product by tailoring its structure.
References
- Makoto Nakaya, Mitsuo Shiraishi, et al., "Solid state relay," Yokogawa Technical Report English Edition, No. 12, 1991, pp. 37-40
- Hiroshi Yuhara, Yoshihiro Okano, et al., "Hybrid recorder HR2300/2400," Yokogawa Technical Report, Vol. 33, No. 4, 1989, pp. 257-260 in Japanese
- Tomonori Komachi, Makoto Nakaya, et al., "Low Output Capacitance Solid State Relay," Yokogawa Technical Report English Edition, No. 23, 1997, pp. 1-4
- Tomonori Komachi, Tadahiko Takayama, Makoto Imamura, "A 1.7 mm-Square 3.2 kV Low Leakage Current Si MOSFET," IEEE IEDM Technical Digest, 2006, pp. 915-918